MEDIATEK Ralink MT7620 - Page 58

PGMT7620_V.1.0_040503
Page 58 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
41. INTENA: Interrupt Enable (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31
RW
GLOBAL
Global Interrupt Enable
Allows local interrupts in this register to be
individually enabled. Set this bit before
enabling interrupts in this register.
0x0
30:20
-
-
Reserved
0x0
19
-
-
Reserved
0x0
18
RW
UHST
USB host interrupt enable
0x0
17
RW
ESW
Ethernet Switch interrupt enable
0x0
16
-
-
Reserved
0x0
15
RW
R2P
R2P interrupt enable
0x0
14
RW
SDHC
SDHC interrupt enable
-
13
-
-
Reserved
-
12
RW
UARTLITE
UARTLITE interrupt enable
0x0
11
RW
SPI
SPI interrupt enable
0x0
10
RW
I2S
I2S interrupt enable
0x0
9
RW
PC
MIPS performance counter interrupt enable
0x0
8
-
-
Reserved
0x0
7
RW
DMA
DMA interrupt enable
0x0
6
RW
PIO
PIO interrupt enable
0x0
5
RW
UART
UART interrupt enable
0x0
4
RW
PCM
PCM interrupt enable
0x0
3
RW
ILL_ACC
Illegal access interrupt enable
0x0
2
RW
WDTIMER
Watchdog timer interrupt enable
0x0
1
RW
TIMER0
Timer 0 interrupt enable
0x0
0
RW
SYSCTL
System control interrupt enable
0x0
NOTE: Where applicable,
1: Enable
42. INTDIS: Interrupt Disable (offset: 0x0038)
Bits
Type
Name
Description
Initial Value
31
RW
GLOBAL
Global Interrupt Disable
Allows local interrupts in this register to be
individually disabled. Set this bit before
disabling interrupts in this register.
0x0
30:20
-
-
Reserved
0x0
19
-
-
Reserved
0x0
18
RW
UHST
USB host interrupt status disable
0x0
17
RW
ESW
Ethernet Switch interrupt disable
0x0
16
-
-
Reserved
0x0
15
RW
R2P
R2P interrupt disable
0x0