MEDIATEK Ralink MT7620 - Page 66

PGMT7620_V.1.0_040503
Page 66 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
50. FCR: FIFO Control Register (offset: 0x0010)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
-
7:6
RW
RXTRIG
Rx Trigger Level
Sets the number of characters contained by the
receive buffer which triggers assertion of the
data ready (DR) interrupt.
0: 1
1: 4
2: 8
3: 14
NOTE: This register is not used if the receive
FIFO is disabled.
0x0
5:4
RW
TXTRIG
Tx Trigger Level
Sets the number of characters contained by the
transmit buffer which triggers the threshold
empty (THRE) interrupt.
0: 1
1: 4
2: 8
3: 12
0x0
3
RW
DMAMODE
Enable DMA transfers
This bit is writeable and readable, but has no
other hardware function.
0x0
2
WO
TXRST
Tx Reset
1: Clears the transmit FIFO and resets the
transmit status. The shift register is not
cleared.
0x0
1
WO
RXRST
Rx Reset
1: Clears the receive FIFO and resets the receive
status. The shift register is not cleared.
0x0
0
RW
FIFOENA
FIFO Enable
Enables Tx and Rx FIFOs. When disabled, the
FIFOs have an effective depth of one character.
0: Disable
1: Enable
NOTE: The FIFO status and data are
automatically cleared when this bit is changed.
0x0
51. LCR: Line Control Register (offset: 0x0014)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7
RW
DLAB
Divisor Latch Access Bit
This bit has no functionality, and is retained for
compatibility only
0x0