MEDIATEK Ralink MT7620 - Page 78

PGMT7620_V.1.0_040503
Page 78 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
66. LSR: Line Status Register (offset: 0x001C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7
RC
ERINFIFO
Error in FIFO
Indicates that a FIFO contains data which was
received with a parity error, framing error, or
break condition.
0x0
6
RC
TEMT
Transmit Shift Register Empty
Indicates that the transmit shift register is
empty. This bit is reset when data is written to
the transmit buffer register (TBR).
0x1
5
RC
THRE
Transmit Holding Register Empty
Indicates that the transmitter holding register is
empty. This bit resets when data is written to
the Tx buffer register (TBR).
0x1
4
RC
BI
Break Interrupt
Indicates that a break is received, that is, when
the RXD signal is at a low state for more than
one character transmission time (from Start Bit
to Stop Bit). Under this condition, a single 0 is
received.
0x1
3
RC
FE
Framing Error
Indicates that a valid Stop Bit is not detected. If
a framing error occurs, the receive buffer will
attempt to re-synchronize by sampling the Start
Bit twice and then receiving the data.
0x0
2
RC
PE
Parity Error
Indicates that the received parity is different
from the expected value.
0x0
1
RC
OE
Overrun Error
Indicates that when a receive overrun occurs.
This happens if a character is received before
the previous character has been read by
firmware.
0x0
0
RC
DR
Data Ready
Indicates that a character is received, and has
been transferred to the receive buffer register.
The bit is reset when all the characters are read
from the receive buffer register.
0x0
NOTE:
0: False
1: True