MEDIATEK Ralink MT7620 - Page 79

PGMT7620_V.1.0_040503
Page 79 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
67. DL: Clock Divider Divisor Latch (offset: 0x0028)
Bits
Type
Name
Description
Initial Value
31:16
-
-
Reserved
0x0
15:0
RW
DL
Divisor Latch
This register is used in the clock divider to
generate the baud clock. The baud rate
(transfer rate in bits per second) is defined as:
Baud rate = system clock frequency / (CLKDIV *
16).
See NOTE below.
0x1
NOTE:
1. In standard 16550 implementation, this register is accessible as two 8-bit halves only. In this implementation,
the DL register is accessible as a single 16-bit entity only.
2. DL[15:0] should be >= 4.
SRC Clock Freq.
Req. Baud Rate (Bd)
DL [15:0]
Error Rate (%)
40 MHz
57 000
44
-0.32%
115 200
22
-1.36%
230 400
11
-1.36%
345 600
7
3.34%
460 800
5
8.51%
68. DLLO: Clock Divider Divisor Latch Low (offset: 0x002C)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
DLLO
Divisor Latch Low
This register is the equivalent to the lower 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In a standard 16550 implementation,
this register is accessible as two 8-bit halves
only. For convenience, the divisor latch is
accessible as a single 16-bit entity via the DL
register.
0x1