MEDIATEK Ralink MT7620 - Page 80

PGMT7620_V.1.0_040503
Page 80 of 523
MT7620 PROGRAMMING GUIDE
Integrated 802.11n MAC/BBP and 2.4 GHz RF/FEM Router-on-a-Chip
69. DLHI: Clock Divider Divisor Latch High (offset: 0x0030)
Bits
Type
Name
Description
Initial Value
31:8
-
-
Reserved
0x0
7:0
RW
DLHI
Divisor Latch High
This register is the equivalent to the upper 8
bits of the DL register. It is provided for 16550
compatibility.
NOTE: In a standard 16550 implementation,
this register is accessible as two 8-bit halves
only. For convenience, the divisor latch is
accessible as a single 16-bit entity via the DL
register.
0x0
70. IFCTL: Interface Control (offset: 0x0034)
Bits
Type
Name
Description
Initial Value
31:1
-
-
Reserved
0x0
0
RW
IFCTL
Open Collector Mode Control
This register controls if the UART Lite TXD
output functions in open collector mode or is
always driven.
0: The output is always driven with the value of
the transmit data signal.
1: The TXD output functions in open collector
mode, where the TXD output is either driven
low (when the transmit data output is active
low) or tri-stated (when the transmit data
output is active high).
0x0