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Mitsubishi Electric MELSEC iQ-R16MTCPU - Page 34

Mitsubishi Electric MELSEC iQ-R16MTCPU
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32
1 MULTIPLE CPU SYSTEM
1.3 Data Communication Between CPU Modules in the Multiple CPU System
The system area is determined by the allocation in the system. Use the user area for communicating user
data.
The refresh (END, I45 executing) area is used with the Multiple CPU refresh. Do not directly change this
area with a program.
Assurance for data communicated between Multiple CPUs
Assurance of data sent between CPUs
Due to the timing of data sent from the self CPU and automatic refresh in any of the other CPUs, old data and new data may
become mixed (data separation).
The following shows the methods for avoiding data separation at communications by refresh.
Data consistency for 32 bit data
Transfer data with refresh method is in units of 32 bits. Since refresh is set in units of 32 bits, 32-bit data does not separate.
For word data, 2 words data can be prevented from separating by using an even number to set the first number of each
device in refresh setting.
Data consistency for 64-bit data
By setting the first number for the device set by refreshing to a multiple of 4, 64-bit data separation can be prevented.
Data consistency for data exceeding 64 bits
In refresh method, data is read in descending order of the setting number in refresh setting parameter. Transfer data
separation can be avoided by using a transfer number lower than the transfer data as an interlock device.

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