16. MULTI-MASTER I
2
C bus INTERFACE
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page 283
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16.13.2 Example of Slave Receive
For example, a slave receives data as shown below when following conditions are met: high-speed clock
mode, SCL frequency of 400 kHz, ACK clock added and addressing format.
1) Set a slave address in the 7 high-order bits in the S0D0 register
2) Set A516 to the S20 register, 0002 to bits ICK4 to ICK2 in the S4D0 register, and 0016 to the S3D0
register to generate an ACK clock and set SCL clock frequency at 400kHz (f1 = 8 MHz, fIIC = f1)
3) Set 0016 to the S10 register to reset transmit/receive mode
4) Set 0816 to the S1D0 register to enable data communication
5) When a START condition is received, addresses are compared
6) •
When the transmitted addresses are all 0 (general call), the ADR0 bit in the S10 register is set to 1
and an I
2
C bus interface interrupt request signal is generated.
•When the transmitted addresses match with the address set in 1), the ASS bit in the S10 register
is set to 1 and an I
2
C bus interface interrupt request signal is generated.
•In other cases, bits ADR0 and AAS are set to 0 and I
2
C bus interface interrupt request signal is not
generated.
7) Write dummy data to the S00 register.
8) After receiving 1-byte data, an ACK-CLK bit is automatically returned and an I
2
C bus interface
interrupt request signal is generated.
9) To determine whether the ACK should be returned depending on contents in the received data, set
dummy data to the S00 register to receive data after setting the WIT bit in te S3D0 register to 1
(enable the I
2
C bus interface interrupt of data receive completion). Because the I
2
C bus interface
interrupt is generated when the 1-byte data is received, set the ACKBIT bit to 1 or 0 to output a
signal from the ACKBIT bit.
10) When receiving more than 1-byte control data, repeat steps 7) and 8) or 7) and 9).
11) When a STOP condition is detected, the communication is ended.
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