20. Flash Memory Version
puorG92/C61M
page 352
854fo7002,03.raM21.1.veR
2110-1010B90JER
20.8.4 Full Status Check
If an error occurs, bits FMR06 to FMR07 in the FMR0 register are set to 1, indicating a specific error.
Therefore, execution results can be comfirmed by verifying these status bits (full status check).
Table 20.7 lists errors and FMR0 register state. Figure 20.14 shows a flow chart of the full status check
and handling procedure for each error.
Table 20.7 Errors and FMR0 Register Status
FMR0 register
(SRD register)
status Error Error occurrence condition
FMR07 FMR06
(SR5) (SR4)
1 1 Command • An incorrect commands is written
sequence error • A value other than xxD016 or xxFF16 is written in the second bus
cycle of the block erase command
(1)
•
When the block erase command is executed on an protected block
• When the program command is executed on protected blocks
1 0 Erase error • The block erase command is executed on an unprotected block
but the program operation is not successfully completed
0 1 Program error • The program command is executed on an unprotected block but
the program operation is not successfully completed
Note 1: The flash memory enters read array mode by writing command code xxFF16 in the second bus
cycle of these commands. The command code written in the first bus cycle becomes invalid.
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