16. MULTI-MASTER I
2
C bus INTERFACE
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page 267
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16.4 I
2
C0 Control Register 0 (S1D0)
The S1D0 register controls data communication format.
16.4.1 Bits 0 to 2: Bit Counter (BC0–BC2)
Bits BC2 to BC0 decide how many bits are in one byte data transferred next. After the selected num-
bers of bits are transferred successfully, I
2
C bus interface interrupt request is gnerated and bits BC2 to
BC0 are reset to 0002. At this time, if the ACK-CLK bit in the S20 register is set to 1 (with ACK clock),
one bit for ACK clock is added to the numbers of bits selected by the BC2 to BC0 bits.
In addition, bits BC2 to BC0 become 0002 even though the START condition is detected and the
address data is transferred in 8 bits.
16.4.2 Bit 3: I
2
C Interface Enable Bit (ES0)
The ES0 bit enables to use the multi-master I
2
C bus interface. When the ES0 bit is set to 0, I
2
C bus
interface is disabled and the SDA and SCL pins are placed in a high-h-impedance state. When the
ES0 bit is set to 1, the interface is enabled.
When the ES0 bit is set to 0, the process is followed.
1)The bits in the S10 register are set as MST = 0, TRX = 0, PIN = 1, BB = 0, AL = 0, AAS = 0,
ADR0 = 0
2)The S00 register cannot be written.
3)The TOF bit in the S4D0 register is set to 0 (time-out detection flag is not detected)
4)The I
2
C system clock (VIIC) stops counting while the internal counter and flags are reset.
16.4.3 Bit 4: Data Format Select Bit (ALS)
The ALS bit determines whether the salve address is recognized. When the ALS bit is set to 0, an
addressing format is selected and a address data is recognized. Only if the comparison is matched
between the slave address stored into the S0D0 register and the received address data or if the
general call is received, the data is transferred. When the ALS bit is set to 1, the free data format is
selected and the slave address is not recognized.
16.4.4 Bit 6: I
2
C bus Interface Reset Bit (IHR)
The IHR bit is used to reset the I
2
C bus interface circuit when the error communication occurs.
When the ES0 bit in the S1D0 register is set to 1 (I
2
C bus interface is enabled), the hardware is reset
by writing 1 to the IHR bit. Flags are processed as follows:
1)The bits in the S10 register are set as MST = 0, TRX = 0, PIN to 1, BB = 0, AL = 0, AAS =
0, and ADR0 = 0
2)The TOF bit in the S4D0 register is set to 0 (time-out detection flag is not detected)
3)The internal counter and flags are reset.
The I
2
C bus interface circuit is reset after 2.5 VIIC cycles or less, and the IHR bit becomes 0 automati-
cally by writing 1 to the IHR bit. Figure 16.10 shows the reset timing.
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