13. Timer S
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page 164
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13.5.2 Phase-Delayed Waveform Output Mode
Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj
register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23
shows an example of phase-delayed waveform mode operation.
Table 13.9 Phase-delayed Waveform Output Mode Specifications
Item Specification
Output waveform • Free-running operation
(bits RST1, RST2, and RST4 in registers G1BCR1 and G1BCR0 are set to 0
(no reset))
Cycle :
"H" and "L" width :
• The base timer is cleared to 0000
16 by matching the base timer with either
following register
(a)
G1PO0 register (enabled by setting RST1 bit to 1, and bits RST4 and RST2 to 0), or
(b)
G1BTRR register (enabled by setting RST4 bit to 1, and bits RST2 and RST1 to 0)
Cycle :
"H" and "L" width :
n : setting value of either G1PO0 register or G1BTRR register
Waveform output start condition The IFEj bit in the G1FE register is set to 1 (channel j function enabled)
Waveform output stop condition The IFEj bit is set to 0 (channel j function disabled)
Interrupt request The G1IRj bit in the interrupt request register is set to 1 when the base timer
value matches the G1POj register value. (See Figure 13.23)
OUTC1j pin
(1)
Pulse signal output pin
Selectable function • Default value set function: Set starting waveform output level
• Inverse output function : Waveform output signal is inversed and provided
from the OUTC1j pin
NOTE:
1. Pins OUTC1
0 to OUTC17.
65536 x 2
f
BT1
65536
f
BT1
2(n+2)
f
BT1
n+2
f
BT1
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