7. Clock Generation Circuit
page 66
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7.7 System Clock Protective Function
When the main clock is selected for the CPU clock source, this function protects the clock from modifica-
tions in order to prevent the CPU clock from becoming halted by run-away.
If the PM21 bit in the PM2 register is set to 1 (clock modification disabled), the following bits are protected
against writes:
• Bits CM02, CM05, and CM07 in CM0 register
• Bits CM10 and CM11 in CM1 register
• CM20 bit in CM2 register
• All bits in the PLC0 register
Before the system clock protective function can be used, the following register settings must be made while
the CM05 bit in the CM0 register is 0 (main clock oscillating) and CM07 bit is 0 (main clock selected for the
CPU clock source):
(1) Set the PRC1 bit in the PRCR register to 1 (enable writes to PM2 register).
(2) Set the PM21 bit in the PM2 register to 1 (disable clock modification).
(3) Set the PRC1 bit in the PRCR register to 0 (disable writes to PM2 register).
Do not execute the WAIT instruction when the PM21 bit is 1.
7.8 Oscillation Stop and Re-oscillation Detect Function
The oscillation stop and re-oscillation detect function detects the re-oscillation after stop of main clock
oscillation circuit. When the oscillation stop and re-oscillation detection occurs, the oscillation stop detect
function is reset or oscillation stop and re-oscillation detection interrupt is generated, depending on the
CM27 bit set in the CM2 register. The oscillation stop detect function is enabled or disabled by the CM20 bit
in the CM2 register. Table 7.8 lists a specification overview of the oscillation stop and re-oscillation detect
function.
Table 7.8 Specification Overview of Oscillation Stop and Re-oscillation Detect Function
Item Specification
Oscillation stop detectable clock and f(XIN) ≥ 2 MHz
frequency bandwidth
Enabling condition for oscillation stop, Set CM20 bit to 1(enable)
re-oscillation detection function
Operation at oscillation stop, •Reset occurs (when CM27 bit =0)
re-oscillation detection •
Oscillation stop, re-oscillation detection interrupt occurs(when CM27 bit =1)
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