Renesas M16C Series - Page 118

A-D Converter
M30240 Group
Rev.1.00 Sep 24, 2003 Page 100 of 360
Figure 1.96: Block diagram of A-D converter
1/2
φ AD
1/2
fAD
A-D conversion rate
selection
(03C1 16 , 03C0 16 )
(03C3
16 , 03C2 16 )
(03C5
16 , 03C4 16 )
(03C7
16 , 03C6 16 )
(03C9
16 , 03C8 16 )
(03CB
16 , 03CA 16 )
(03CD
16 , 03CC 16 )
(03CF
16 , 03CE 16 )
CKS1=1
CKS0=0
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
A-D register 4(16)
A-D register 5(16)
A-D register 6(16)
A-D register 7(16)
Resistor ladder
Successive conversion register
AN 0
AN 1
AN 2
AN 3
AN 5
AN 6
AN 7
A-D control register 0 (address 03D6 16 )
A-D control register 1 (address 03D7
16 )
V
ref
V IN
Data bus high-order
Data
bus
low-order
VREF
AN 4
VCUT=0
AV SS
VCUT=1
CKS0=1
CKS1=0
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
Decoder
Comparator
Addresses