Renesas M16C Series - Page 215

Clock-Synchronous Serial I/O
M30240 Group
Rev.1.00 Sep 24, 2003 Page 197 of 360
Figure 2.53: Set-up procedure of reception in clock-synchronous serial I/O mode (2)
Writing dummy data
UART0 transmit buffer register [Address 03A3 16, 03A216] U0TB
UART1 transmit buffer register [Address 03AB
16, 03AA16] U1TB
UART2 transmit buffer register [Address 037B
16, 037A16] U2TB
Setting dummy data
b7 b0 b7 b0
(b15) (b8)
Checking completion of reception
UARTi transmit/receive control register 1(i = 0 to 2) [Address 03A5 16, 03AD16, 037D16]
UiC1 (i = 0 to 2)
b7 b0
Receive complete flag
0 : No data present in receive buffer register
1 : Data present in receive buffer register
Start reception
Processing after reading out reception data
Continued from the previous page
Checking error
UART0 receive buffer register [Address 03A7 16, 03A616]U0RB
UART1 receive buffer register [Address 03AF
16, 03AE16]U1RB
UART2 receive buffer register [Address 037F
16, 037E16]U2RB
Overrun error flag
0 : No overrun error
1 : Overrun error found
b7 b0 b7 b0
(b15) (b8)
Receive data
Reception enabled
UARTi transmit/receive control register 1(i = 0 to 2) [Address 03A5 16, 03AD16, 037D16]
UiC1 (i = 0 to 2)
Transmit enable bit
1 : Transmit enabled
b7 b0
Receive enable bit
1 : Receive enabled
11