Programmable I/O Ports
M30240 Group
Rev.1.00 Sep 24, 2003 Page 286 of 360
Figure 2.134: Port 2 and PWM drive capacity registers
Port 2 Drive Capacity Register
Symbol Address When reset
P2DR
03FA16 0016
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
P2DR0 P20 LED drive capacity
P2DR1 P2
1 LED drive capacity
P2DR2 P2
2 LED drive capacity
P2DR3 P2
3 LED drive capacity
P2DR4 P24 LED drive capacity
P2DR5 P2
5 LED drive capacity
P2DR6 P2
6 LED drive capacity
P2DR7 P2
7 LED drive capacity
The N-channel high-drive capacity
is activated for the corresponding
bit.
0 : Normal drive
1 : N-channel high drive
Timer A Output drive capacity register
Symbol Address When reset
TADR
03FB16 0016
Bit name Function Bit symbol WR
b7 b6 b5 b4 b3 b2 b1 b0
TADR0 TA0OUT drive capacity
TADR1 TA1OUT drive capacity
TADR2 TA2OUT drive capacity
TADR3 TA3OUT drive capacity
TADR4 TA4OUT drive capacity
High-drive capacity is activated for
the corresponding TAiOUT pin.
0 : Normal drive
1 : High drive
Nothing is assigned. These bits can neither be
set nor reset.
When read, their value is 0.
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