Overview of Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 337 of 360
The following are conditions under which an interrupt is accepted:
• interrupt enable flag (I flag) = 1
• interrupt request bit = 1
• interrupt priority level > IPL
Table 4.4: Settings of interrupt priority levels
Table 4.5: Interrupt levels enabled according to the contents of the IPL
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt
in the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect on the instruction that
is executed 2 clock cycles after the last clock cycle involved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes effect
on the instruction that is executed 3 cycles after the last clock cycle involved in the instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect on the instruction that is executed 2 clock cycles after the last clock cycle involved in the in-
struction used.
Interrupt priority level select bit Interrupt priority level Priority order
b2 b1 b0
0 0 0 Level 0 (interrupt disabled)
001Level 1 Low
010Level 2
011Level 3
100Level 4
101Level 5
110Level 6
1 1 1 Level 7 High
IPL Enabled interrupt priority levels
IPL
2
IPL
1
IPL
0
0 0 0 Interrupt levels 1 and above are enabled
0 0 1 Interrupt levels 2 and above are enabled
0 1 0 Interrupt levels 3 and above are enabled
0 1 1 Interrupt levels 4 and above are enabled
1 0 0 Interrupt levels 5 and above are enabled
1 0 1 Interrupt levels 6 and above are enabled
1 1 0 Interrupt levels 7 and above are enabled
1 1 1 All maskable interrupts are disabled
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