Overview of Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 343 of 360
4.1.4.3 Interrupt Routine Return
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of the interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program
that was being executed before the acceptance of the interrupt request, so that the suspended pro-
cess resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
4.1.5 Multiple Interrupts
The following occurs when branching to an interrupt routine:
• The interrupt enable flag (I flag) is set to “0” (the interrupt is disabled).
• The interrupt request bit of the accepted interrupt is set to “0”.
• The processor interrupt priority level (IPL) is assigned to the same interrupt priority level as assigned
to the accepted interrupt.
Setting the interrupt enable flag (I flag) to “1” within an interrupt routine allows an interrupt request
assigned a priority higher than the IPL to be accepted. Figure 4.9 shows the scheme of multiple
interrupts.
An interrupt request that is not accepted because of low priority will be held. If the following condition
is met when the REIT instruction returns the IPL and the interrupt priority is determined, then the
interrupt request being held is accepted.
Interrupt priority level of the interrupt request being held > IPL contents
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