DMAC
M30240 Group
Rev.1.00 Sep 24, 2003 Page 61 of 360
Figure 1.53: Block diagram of DMAC
Figure 1.54: DMAC register (1)
Data bus low-order bits
DMA latch high-order bits DMA latch low-order bits
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20)
Data bus high-order bits
Address bus
DMA1 destination pointer DAR1 (20)
DMA1 source pointer SAR1 (20)
DMA1 forward address pointer (20)
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
(addresses 0029
16
, 0028
16
)
(addresses 0039
16
, 0038
16
)
(addresses 0022
16
to 0020
16
)
(addresses 0026
16
to 0024
16
)
(addresses 0032
16
to 0030
16
)
(addresses 0036
16
to 0034
16
)
Note: Pointer is incremented by
a
a DMA request.
(Note)
(Note)
DMAi request cause select register
Symbol
Address
When reset
DMiSL (i=0,1) 03B8
16
, 03BA
16
00
16
Function (Note)
Bit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DMA request cause
select bits
DSEL0
RW
DSEL1
DSEL2
DSEL3
Nothing is assigned.
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
DSR
b3 b2 b1 b0
0 0 0 0 : Falling edge of INT0 /INT1pin (Note 1)
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4
0 1 1 1 : Timer B0
1 0 0 0 : Timer B1
1 0 0 1 :
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit/UART receive (Note 2)
Bit name
Write "0" when writing to these bits. If read, the value is "0".
USB0/USB1 (Note 3)
Note 1: Address 03B8
16
is for INT0, 3BA
16
is for INT1.
Note 2: Address 03B8
16
is for UART1 transmit, 03BA
16
is for UART1 receive.
Note 3: Address 03B8
16
is for USB0, 03BA
16
is for USB1.
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