DMAC
M30240 Group
Rev.1.00 Sep 24, 2003 Page 62 of 360
Figure 1.55: DMAC register (2)
DMAi control register
Symbol
Address
When reset
DMiCON(i=0,1)
002C
16, 003C16
00000X002
Bit name FunctionBit symbol
Transfer unit bit select bit
b7 b6 b5 b4 b3 b2 b1 b0
0 : 16 bits
1 : 8 bits
DMBIT
RW
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMA request bit (Note 1)
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forward
DMA enable bit
Source address direction
select bit (Note 3)
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Nothing is assigned.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
(Note 2)
Write "0" when writing to these bits. If read, the value is "0".
To Next Page
Loading...
