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Renesas RL78/F13 - Page 1189

Renesas RL78/F13
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RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1157
Dec 10, 2015
ERR flag (error detection flag)
The ERR flag is set to 1 upon detection of an error (any of the LESTn register flags is 1). Here, an interrupt is generated if
the ERRIE bit in the LIEn register is 1 (interrupt is enabled). Note that when an error is detected with the ERR flag set to 1,
an interrupt is not generated. To clear the bit to 0, write 0 to the RPER, IPER ,CSER, SFER, FER, TER, and BER flags in
the LESTn register. This clears the ERR flag to 0.
D1RC flag (successful data 1 reception flag)
Only 0 can be written to the D1RC flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The D1RC flag is set to 1 upon completion of data 1 reception. Here, an interrupt is not generated. To clear the bit to 0, write
0 to the bit.
When response data of 9 bytes or more is to be received, this bit is set to 1 each time data 1 of a data group (variable from
0 to 8 bytes) is received. Write 0 before starting reception of the next data group.
HTRC flag (successful header transmission flag)
Only 0 can be written to the HTRC flag; when 1 is written, the bit retains the value that has been retained before 1 is written.
The HTRC flag is set to 1 upon completion of header transmission. Here, an interrupt is generated if the SHIE bit in the LIEn
register is 1 (interrupt is enabled). Note that when header reception is completed with the HTRC flag set to 1, an interrupt is
not generated. To clear the bit to 0, write 0 to the bit.
After the reception of a header, clear this bit after reading it as 1 so that a new header will be detectable.

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