Renesas RL78/F13 User Manual

RL78/F13, F14 CHAPTER 23 STANDBY FUNCTION
R01UH0368EJ0210 Rev.2.10 1529
Dec 10, 2015
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation,
the program branches.
Figure 23-5. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
(2) When high-speed on-chip oscillator clock is used as CPU clock
(3) When subsystem clock or low-speed on-chip oscillator clock is used as CPU clock
Note For the reset processing time, see CHAPTER 25 POWER-ON-RESET CIRCUIT.
HALT
instruction
Reset signal
High-speed

system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Normal operation
(high-speed on-chip
oscillator clock)

Starting X1 oscillation is
specified by software.
Reset processing
Note
HALT
instruction
Reset signal
High-speed on-chip
oscillator clock
Normal operation
(high-speed on-chip
oscillator clock)
HALT mode
Reset
period
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
Reset processing
Note
HALT
instruction
Operating modeHALT modeOperating mode
Oscillation
High-speed system clock,
High-speed on-chip oscillator clock,
PLL clock,
low-speed on-chip oscillator clock,
or subsystem clock
Status of CPU
Standby
release signal
Interrupt
request
Wait
Note

Renesas RL78/F13 Specifications

General

Brand	Renesas
Model	RL78/F13
Category	Computer Hardware
Language	English