RL78/F13, F14 CHAPTER 25 POWER-ON-RESET CIRCUIT
R01UH0368EJ0210 Rev.2.10 1557
Dec 10, 2015
Figure 25-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (1/2)
(1) When the externally input reset signal on the RESET pin is used
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
2. The high-speed on-chip oscillator clock and a high-speed system clock or subsystem clock can be selected
as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC)
to confirm the lapse of the oscillation stabilization time. To use the XT1 clock, use the timer function for
confirmation of the lapse of the stabilization time.
3. The time until normal operation starts includes the following reset processing time when the external reset is
released (after the first release of POR) after the RESET signal is driven high (1) as well as the voltage
stabilization wait time after V
POR (1.56 V, typ.) is reached.
Reset processing time when the external reset is released is shown below.
After the first release of POR: 0.672 ms (typ.), 0.832 ms (max.) (when the LVD is in use)
0.399 ms (typ.), 0.519 ms (max.) (when the LVD is off)
4. Reset processing time when the external reset is released after the second release of POR is shown below.
After the second release of POR: 0.531 ms (typ.), 0.675 ms (max.) (when the LVD is in use)
0.259 ms (typ.), 0.362 ms (max.) (when the LVD is off)
5. After power is supplied, the reset state must be retained until the operating voltage becomes in the range
defined in the AC characteristics in CHAPTER 34 to CHAPTER 36 ELECTRICAL SPECIFICATIONS. This
is done by controlling the externally input reset signal. After power supply is turned off, this LSI should be
placed in the STOP mode, or in the reset state by utilizing the voltage detection circuit or externally input
reset signal, before the voltage falls below the operating range. When restarting the operation, make sure
that the operation voltage has returned within the range of operation.
Remark V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
0 V
CPU
Note 5 Note 5
Reset processing time
when external reset is released
Note 3
Reset processing time
when external reset is released
Note 4
Voltage stabilization wait
0.99 ms (TYP.), 2.30
ms (MAX.)
High-speed on-chip
oscillator clock (f
IH)
High-speed
system clock (f
MX)
(when X1 oscillation
is selected)
Starting
oscillation is
specified
by software
Operation
stops
Supply voltage
(V
DD)
Wait for oscillation
accuracy stabilization
Note 1
Wait for oscillation
accuracy stabilization
Note 1
Normal operation
(high-speed on-chip
oscillator clock)
Note 2
Normal operation
(high-speed on-chip
oscillator clock)
Note 2
Reset
period
(oscillation
stop)
Internal reset signal
RESET pin
Operating voltage
range lower limit
V
PDR
=
1.55 V (TYP.)
V
POR
=
1.56 V (TYP.)
Starting
oscillation is
specified
by software
10 µs or more
Operation
stops
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