RL78/F13, F14 CHAPTER 3 CPU ARCHITECTURE
R01UH0368EJ0210 Rev.2.10 163
Dec 10, 2015
Table 3-6. Extended SFR (2nd SFR) List (12/32)
Address Special Function Register (2nd SFR) Name Symbol R/W Manipulable Bit Range
After
reset
1-bit 8-bit 16-bit
F038EH CAN global test control register GTSTCTRL – R/W – √ – 00H
F038FH – – –
F0394H CAN global test protection unlock register GLOCKK W – – √ 0000H
F0395H – –
F03A0H CAN receive rule entry register 0AL
Note 1
GAFLIDL0L GAFLIDL0 R/W – √ √ 0000H
F03A1H GAFLIDL0H – √
F03A0H CAN receive buffer register 0AL
Note 2
RMIDL0L RMIDL0 R – √ √ 0000H
F03A1H RMIDL0H – √
F03A2H CAN receive rule entry register 0AH
Note 1
GAFLIDH0L GAFLIDH0 R/W – √ √ 0000H
F03A3H GAFLIDH0H – √
F03A2H CAN receive buffer register 0AH
Note 2
RMIDH0L RMIDH0 R – √ √ 0000H
F03A3H RMIDH0H – √
F03A4H CAN receive rule entry register 0BL
Note 1
GAFLML0L GAFLML0 R/W – √ √ 0000H
F03A5H GAFLML0H – √
F03A4H CAN receive buffer register 0BL
Note 2
RMTS0L RMTS0 R – √ √ 0000H
F03A5H RMTS0H – √
F03A6H CAN receive rule entry register 0BH
Note 1
GAFLMH0L GAFLMH0 R/W – √ √ 0000H
F03A7H GAFLMH0H – √
F03A6H CAN receive buffer register 0BH
Note 2
RMPTR0L RMPTR0 R – √ √ 0000H
F03A7H RMPTR0H – √
F03A8H CAN receive rule entry register 0CL
Note 1
GAFLPL0L GAFLPL0 R/W – √ √ 0000H
F03A9H GAFLPL0H – √
F03A8H CAN receive buffer register 0CL
Note 2
RMDF00L RMDF00 R – √ √ 0000H
F03A9H RMDF00H – √
F03AAH CAN receive rule entry register 0CH
Note 1
GAFLPH0L GAFLPH0 R/W – √ √ 0000H
F03ABH GAFLPH0H – √
F03AAH CAN receive buffer register 0CH
Note 2
RMDF10L RMDF10 R – √ √ 0000H
F03ABH RMDF10H – √
F03ACH CAN receive rule entry register 1AL
Note 1
GAFLIDL1L GAFLIDL1 R/W – √ √ 0000H
F03ADH GAFLIDL1H – √
F03ACH CAN receive buffer register 0DL
Note 2
RMDF20L RMDF20 R – √ √ 0000H
F03ADH RMDF20H – √
F03AEH CAN receive rule entry register 1AH
Note 1
GAFLIDH1L GAFLIDH1 R/W – √ √ 0000H
F03AFH GAFLIDH1H – √
F03AEH CAN receive buffer register 0DH
Note 2
RMDF30L RMDF30 R – √ √ 0000H
F03AFH RMDF30H – √
F03B0H CAN receive rule entry register 1BL
Note 1
GAFLML1L GAFLML1 R/W – √ √ 0000H
F03B1H GAFLML1H –
√
Notes 1. These registers are allocated to the RAM window 0 for the CAN module (receive rule and CAN RAM test register).
When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to the RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.
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