SONIX SN32F264 - I2 C N Status Register (I2 Cn_Stat) (N=0)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 101 Version 1.5
 The address in the Slave Address register has been received.
 The General Call address has been received while the General Call
bit (GC) in the ADR register is set.
 A data byte has been received while the I2C is in the master
receiver mode.
 A data byte has been received while the I2C is in the addressed
slave receiver mode.
HW will clear after issuing ACK automatically.
1
NACK
Assert NACK (HIGH level to SDA) flag.
0: No function.
1: An NACK will be returned during the acknowledge clock pulse on SCLn
when
 A data byte has been received while the I2C is in the master
receiver mode.
HW will clear after issuing NACK automatically.
R/W
0
0
Reserved
R
0
9.7.2 I2C n Status register (I2Cn_STAT) (n=0)
Address Offset: 0x04
Check this register when I2C interrupt occurs, and all status will be cleared automatically by writing I2Cn_CTRL or
I2Cn_TXDATA register.
While I2CIF =1, the low period of the serial clock on the SCL line is stretched, and the serial transfer is suspended.
When SCL is HIGH, it is unaffected by the state of I2CIF.
Following events will trigger I2C interrupt if I2C interrupt is enabled in NVIC interrupt controller.
START/Repeat START condition
STOP condition
Timeout
Data byte transmitted or received
ACK Transmit or received
NACK Transmit or received
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15
I2CIF
I2C Interrupt flag.
0: I2C status doesn’t change.
1: ReadI2C status changes.
WriteClear this flag.
R/W
0
14:10
Reserved
R
0
9
TIMEOUT
Time-out status.
0: No Timeout.
1: Timeout.
R
0
8
LOST_ARB
Lost arbitration.
0: Not lost arbitration.
1: Lost arbitration.
R
0
7
SLV_TX_HIT
0: No matched slave address.
1: Slave address hit, and is called for TX in slave mode.
R
0
6
SLV_RX_HIT
0: No matched slave address.
1: Slave address hit, and is called for RX in slave mode.
R
0
5
MST
Master/Slave status.
0: I2C is in Slave state.
1: I2C is in Master state.
R
0
4
START_DN
Start done status.
0: No START bit.
1: MASTER mode a START bit was issued.
SLAVE modea START bit was received.
R
0
3
STOP_DN
Stop done status.
0: No STOP bit.
1: MASTER modea STOP condition was issued.
R
0