SONIX SN32F264 - Flash Data Register (FLASH_DATA); Flash Address Register (FLASH_ADDR); Flash Checksum Register (FLASH_CHKSUM)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 123 Version 1.5
1
PER
Page Erase chosen.
This bit is set only by SW and reset when the BUSY bit resets.
R/W
0
0
PG
Flash Programming chosen.
This bit is set only by SW and reset when the BUSY bit resets.
R/W
0
11.11.4 Flash Data register (FLASH_DATA)
Address offset: 0x0C
For Page Program operations, this should be updated by SW to indicate the data to be programmed.
Bit
Name
Description
Attribute
Reset
31:0
DATA[31:0]
Data to be programmed.
R/W
0
11.11.5 Flash Address register (FLASH_ADDR)
Address offset: 0x10
The Flash address to be erased or programmed should be updated by SW, and the PG bit or PER bit shall be set
before filling in the Flash address.
 Note: Write access to this register is blocked when the BUSY bit in the FLASH_STATUS register is set.
Bit
Name
Description
Attribute
Reset
31:0
FAR[31:0]
Flash Address
Choose the Flash address to erase when Page Erase is selected, or to
program when Page Program is selected.
R/W
0
11.11.6 Flash Checksum register (FLASH_CHKSUM)
Address offset: 0x14
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
CHKSUM[15:0]
Checksum of User ROM.
R
0