SONIX SN32F264 - AHB Clock Prescale Register (SYS0_AHBCP); System Reset Status Register (SYS0_RSTST)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 42 Version 1.5
Other: Reserved
3.3.4 AHB Clock Prescale register (SYS0_AHBCP)
Address Offset: 0x10
Bit
Name
Description
Attribute
Reset
31:3
Reserved
R
0
2:0
AHBPRE[2:0]
AHB clock source prescale value
000: SYSCLK / 1
001: SYSCLK / 2
010: SYSCLK / 4
011: SYSCLK / 8
100: SYSCLK / 16
101: SYSCLK / 32
110: SYSCLK / 64
111: SYSCLK / 128
Other: Reserved
R/W
010b
3.3.5 System Reset Status register (SYS0_RSTST)
Address Offset: 0x14
This register contains the reset source.
Bit
Name
Description
Attribute
Reset
31:5
Reserved
R
0
4
PORRSTF
POR reset flag
Set by HW when a POR reset occurs.
0: ReadNo POR reset occurred
WriteClear this bit
1: POR reset occurred.
R/W
1
3
EXTRSTF
External reset flag
Set by HW when a reset from the RESET pin occurs.
0: ReadNo reset from RESET pin occurred
WriteClear this bit
1: Reset from RESET pin occurred.
R/W
0
2
LVDRSTF
LVD reset flag
Set by HW when a LVD reset occurs.
0: ReadNo LVD reset occurred
WriteClear this bit
1: LVD reset occurred.
R/W
0
1
WDTRSTF
WDT reset flag
Set by HW when a WDT reset occurs.
0: ReadNo watchdog reset occurred
WriteClear this bit
1: Watchdog reset occurred.
R/W
0
0
SWRSTF
Software reset flag
Set by HW when a software reset occurs.
0: ReadNo software reset occurred
WriteClear this bit
1: Software reset occurred.
R/W
1