SONIX SN32F264 - SPI N Interrupt Clear Register (Spin; SPI N Data Register (Spin _DATA) (N=0); SPI N Data Fetch Register (Spin

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 95 Version 1.5
8.6.7 SPI n Interrupt Clear register (SPIn _IC) (n=0)
Address Offset: 0x18
Bit
Name
Description
Attribute
Reset
31:4
Reserved
R
0
3
TXFIFOTHIC
0: No effect.
1: Clear TXFIFOTHIF bit.
W
0
2
RXFIFOTHIC
0: No effect
1: Clear RXFIFOTHIF bit.
W
0
1
RXTOIC
0: No effet.
1: Clear RXTOIF bit..
W
0
0
RXOVFIC
0: No effet.
1: Clear RXOVFIF bit..
W
0
8.6.8 SPI n Data register (SPIn _DATA) (n=0)
Address Offset: 0x1C
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
DATA[15:0]
Write
SW can write data to be sent in a future frame to this register when
TX_FULL = 0 in SPIn_STAT register (TX FIFO is not full). If the TX FIFO
was previously empty and the SPI controller is not busy on the bus,
transmission of the data will begin immediately. Otherwise the data written
to this register will be sent as soon as all previous data has been sent (and
received).
Read
SW can read data from this register when RX_EMPTY=0 in SPIn_STAT
registe (Rx FIFO is not empty). When SW reads this register, the SPI
controller returns data from the least recent frame in the RX FIFO. If the
data length is less than 16 bit, the data is right-justified in this field with
higher order bits filled with 0s.
R/W
0
8.6.9 SPI n Data Fetch register (SPIn _DF) (n=0)
Address Offset: 0x20
Bit
Name
Description
Attribute
Reset
31:1
Reserved
R
0
0
DF
SPI data fetch control bit.
0: Disable.
1: Enable.
R/W
0