SONIX SN32F264 - SPI N Control Register 1 (Spin_Ctrl1) (N=0); SPI N Clock Divider Register (Spin _CLKDIV) (N=0); SPI N Status Register (Spin _STAT) (N=0)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 93 Version 1.5
1: Enable and HW switches I/O configurations refer to FORMAT bit
directly.
8.6.2 SPI n Control register 1 (SPIn_CTRL1) (n=0)
Address Offset: 0x04
Bit
Name
Description
Attribute
Reset
31:3
Reserved
R
0
2
CPHA
Clock phase for edge sampling.
0: Data changes at clock falling edge, latches at clock rising edge when
CPOL = 0; Data changes at clock rising edge, latches at clock falling
edge when CPOL = 1.
1: Data changes at clock rising edge, latches at clock falling edge when
CPOL = 0; Data changes at clock falling edge, latches at clock rising
edge when CPOL = 1.
R/W
0
1
CPOL
Clock polarity selection bit.
0: SCK idles at Low level.
1: SCK idles at High level.
R/W
0
0
MLSB
MSB/LSB selection bit
0: MSB transmit first.
1: LSB transmit first.
R/W
0
8.6.3 SPI n Clock Divider register (SPIn _CLKDIV) (n=0)
Address Offset: 0x08
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
DIV[7:0]
SPIn clock divider
0: SCK = SSPn_PCLK / 2
1: SCK = SSPn_PCLK / 4
2: SCK = SSPn_PCLK / 6
X: SCK = SSPn_PCLK / (2X+2)
R/W
0
8.6.4 SPI n Status register (SPIn _STAT) (n=0)
Address Offset: 0x0C
Bit
Name
Description
Attribute
Reset
31:7
Reserved
R
0
6
RXFIFOTHF
RX FIFO threshold flag.
0: Data in RX FIFO ≤ RXFIFOTH.
1: Data in RX FIFO > RXFIFOTH.
R
0
5
TXFIFOTHF
TX FIFO threshold flag.
0: Data in TX FIFO > TXFIFOTH.
1: Data in TX FIFO ≤ TXFIFOTH.
R
1
4
BUSY
Busy flag.
0: SPI controller is idle.
1: SPI controller is transferring.
R
0
3
RX_FULL
RX FIFO full flag.
0: RX FIFO is NOT full.
1: RX FIFO is full.
R
0
2
RX_EMPTY
RX FIFO empty flag.
0: RX FIFO is NOT empty.
1: RX FIFO is empty.
R
1
1
TX_FULL
TX FIFO full flag.
0: TX FIFO is NOT full.
R
0