SONIX SN32F264 - System Control Registers 1; AHB Clock Enable Register (SYS1_AHBCLKEN)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 46 Version 1.5
3.4 SYSTEM CONTROL REGISTERS 1
Base Address: 0x4005 E000
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN)
Address Offset: 0x00
The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks.
 Note:
1. When the clock is disabled, the peripheral register values may not be readable by SW and the
value returned is always 0x0.
2. HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0.
Bit
Name
Description
Attribute
Reset
31
Reserved
R
0
30:28
CLKOUTSEL[2:0]
Clock output source
000: Disable
001: ILRC clock
100: HCLK
101: IHRC clock
Others: Reserved.
R/W
0
27:25
Reserved
R
0
24
WDTCLKEN
Enables clock for WDT.
0: Disable
1: Enable
R/W
1
23:22
Reserved
R
0
21
I2C0LKEN
Enables clock for I2C0.
0: Disable
1: Enable
R/W
0
20:13
Reserved
R
0
12
SPI0CLKEN
Enables clock for SPI0.
0: Disable
1: Enable
R/W
0
11:8
Reserved
R
0
7
CT16B1CLKEN
Enables clock for CT16B1.
0: Disable
1: Enable
R/W
0
6
CT16B0CLKEN
Enables clock for CT16B0.
0: Disable
1: Enable
R/W
0
5
Reserved
R
0
4
USBCLKEN
Enable clock for USB
0: Disable
1: Enable
R/W
0
3
P3CLKEN
Enables clock for P3.
0: Disable
1: Enable
R/W
1
2
P2CLKEN
Enables clock for P2.
0: Disable
1: Enable
R/W
1
1
P1CLKEN
Enables clock for P1.
0: Disable
1: Enable
R/W
1
0
P0CLKEN
Enables clock for P0.
R/W
1