SONIX SN32F264 - USB Device Address Register (USB_ADDR); USB Configuration Register (USB_CFG)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 111 Version 1.5
22
EP0_INC
0: No effect.
1: Clear EP0_IN bit.
W
0
21
EP0_OUTC
0:.No effect.
1: Clear EP0_OUT bit.
W
0
20
EP0_IN_STALLC
0: No effect.
1: Clear EP0_IN_STALL bit.
W
0
19
EP0_OUT_STALLC
0: No effect.
1: Clear EP0_OUT_STALL bit.
W
0
18
ERR_SETUPC
0: No effect.
1: Clear ERR_SETUP bit.
W
0
17
ERR_TIMEOUTC
0: No effect.
1: Clear ERR_TIMEOUT bit.
W
0
16:12
Reserved
R
-
11
EP4_ACKC
0: No effect.
1: Clear EP4_ACK bit.
W
0
10
EP3_ACKC
0: No effect.
1: Clear EP3_ACK bit.
W
0
9
EP2_ACKC
0: No effect.
1: Clear EP2_ACK bit.
W
0
8
EP1_ACKC
0: No effect.
1: Clear EP1_ACK bit.
W
0
7:4
Reserved
R
-
3
EP4_NAKC
0: No effect.
1: Clear EP4_NAK bit.
W
0
2
EP3_NAKC
0: No effect.
1: Clear EP3_NAK bit.
W
0
1
EP2_NAKC
0: No effect.
1: Clear EP2_NAK bit.
W
0
0
EP1_NAKC
0: No effect.
1: Clear EP1_NAK bit.
W
0
10.9.4 USB Device Address Register (USB_ADDR)
Address Offset: 0x0C
Reset value: 0x0000 0000
Bit
Name
Description
Attribute
Reset
31:7
Reserved
R
0
6:0
UADDR
USB device’s address.
R/W
0
10.9.5 USB Configuration Register (USB_CFG)
Address offset: 0x10
Reset value: 0x0000 0000
Bit
Name
Description
Attribute
Reset
31
VREG33_EN
Internal VREG33 output function. If VREG33_EN is disabled, VREG33
will be switched to IC_VDD.
0: Disable
1: Enable
R/W
1
30
PHY_EN
PHY transceiver function. PHY will be automatically disabled if entering
sleep mode, deep-sleep mode, and deep-power down mode.
0: Disable PHY transceiver function.
1: Enable PHY transceiver function.
R/W
0