SONIX SN32F264 - Nvic Registers; IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER); IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 27 Version 1.5
31
Settable
IRQ15/ I2C0IRQ
I2C0
0x0000 007C
32
Settable
IRQ16/CT16B0IRQ
CT16B0
0x0000 0080
33
Settable
IRQ17/CT16B1IRQ
CT16B1
0x0000 0084
34
Settable
IRQ18/
0x0000 0088
35
Settable
IRQ19/
0x0000 008C
36
Settable
IRQ20/
0x0000 0090
37
Settable
IRQ21/
0x0000 0094
38
Settable
IRQ22/
0x0000 0098
39
Settable
IRQ23/
0x0000 009C
40
Settable
IRQ24/
0x0000 00A0
41
Settable
IRQ25/WDTIRQ
WDT
0x0000 00A4
42
Settable
IRQ26/LVDIRQ
LVD
0x0000 00A8
43
Settable
IRQ27/
0x0000 00AC
44
Settable
IRQ28/P3IRQ
GPIO interrupt status of port 3
0x0000 00B0
45
Settable
IRQ29/P2IRQ
GPIO interrupt status of port 2
0x0000 00B4
46
Settable
IRQ30/P1IRQ
GPIO interrupt status of port 1
0x0000 00B8
47
Settable
IRQ31/P0IRQ
GPIO interrupt status of port 0
0x0000 00BC
2.3.2 NVIC REGISTERS
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)
Address: 0xE000 E100 (Refer to Cortex-M0 Spec.)
The ISER enables interrupts, and shows the interrupts that are enabled.
Bit
Name
Description
Attribute
Reset
31:0
SETENA[31:0]
Interrupt set-enable bits.
Write 0: No effect
1: Enable interrupt.
Read 0: Interrupt disabled
1: Interrupt enabled.
R/W
0
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)
Address: 0xE000 E180 (Refer to Cortex-M0 Spec.)
The ICER disables interrupts, and shows the interrupts that are enabled.
Bit
Name
Description
Attribute
Reset
31:0
CLRENA[31:0]
Interrupt clear-enable bits.
Write 0: No effect
1: Disable interrupt.
R/W
0