SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 70 Version 1.5
6.7.9 CT16Bn Match Control register 3 (CT16Bn_MCTRL3) (n=1)
Address Offset: 0x1C
Stop MR23: TC and PC will stop and CEN bit will be cleared if MR23
matches TC..
0: Disable
1: Enable.
Enable reset TC when MR23 matches TC.
0: Disable.
1: Enable.
Enable generating an interrupt based on CM[2:0] when MR23 matches the
value in the TC.
0: Disable.
1: Enable.
Stop MR22: TC and PC will stop and CEN bit will be cleared if MR22
matches TC.
0: Disable.
1: Enable.
Enable reset TC when MR22 matches TC.
0: Disable.
1: Enable.
Enable generating an interrupt based on CM[2:0] when MR22 matches the
value in the TC.
0: Disable.
1: Enable.
Stop MR21: TC and PC will stop and CEN bit will be cleared if MR21
matches TC.
0: Disable.
1: Enable.
Enable reset TC when MR21 matches TC.
0: Disable.
1: Enable.
Enable generating an interrupt based on CM[2:0] when MR21 matches the
value in the TC.
0: Disable.
1: Enable.