SONIX SN32F264 - GPIO Port N Interrupt Sense Register (Gpion_Is) (N=0,1,2,3); GPIO Port N Interrupt Both-Edge Sense Register (Gpion_Ibs) (N=0,1,2,3); GPIO Port N Interrupt Event Register (Gpion_Iev) (N=0,1,2,3)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 56 Version 1.5
register keep low)
7:6
CFG3[1:0]
Configuration of Pn.3
00: Pull-up resistor enabled.
01: Reserved.
10: Inactive. (no pull-up resistor enabled, Schmitt trigger enabled).
11: Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data
register keep low)
R/W
10b
5:4
CFG2[1:0]
Configuration of Pn.2
00: Pull-up resistor enabled.
01: Reserved.
10: Inactive. (no pull-up resistor enabled, Schmitt trigger enabled).
11: Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data
register keep low)
R/W
10b
3:2
CFG1[1:0]
Configuration of Pn.1
00: Pull-up resistor enabled.
01: Reserved.
10: Inactive. (no pull-up resistor enabled, Schmitt trigger enabled).
11: Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data
register keep low)
R/W
10b
1:0
CFG0[1:0]
Configuration of Pn.0
00: Pull-up resistor enabled.
01: Reserved.
10: Inactive. (no pull-up resistor enabled, Schmitt trigger enabled).
11: Inactive. (no pull-up resistor enabled, Schmitt trigger disabled, Data
register keep low)
R/W
10b
5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3)
Address offset: 0x0C
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IS[15:0]
Selects interrupt on pin x as level or edge sensitive. (x = 0 to 15)
0: Interrupt on Pn.x is configured as edge sensitive.
1: Interrupt on Pn.x is configured as event sensitive.
R/W
0
5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3)
Address offset: 0x10
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IBS[15:0]
Selects interrupt on Pn.x to be triggered on both edges. (x = 0 to 15)
0: Interrupt on Pn.x is controlled through register GPIOn_IEV.
1: Both edges on Pn.x trigger an interrupt.
R/W
0
5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3)
Address offset: 0x14
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IEV[15:0]
Selects interrupt on pin x to be triggered rising or falling edges. (x = 0 to 15)
0: Depending on setting in register GPIOn_IS, Rising edges or HIGH level
on Pn.x trigger an interrupt.
R/W
0