SONIX SN32F264 - LVD Control Register (SYS0_LVDCTRL); External RESET Pin Control Register (SYS0_EXRSTCTRL); SWD Pin Control Register (SYS0_SWDCTRL)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 43 Version 1.5
3.3.6 LVD Control register (SYS0_LVDCTRL)
Address Offset: 0x18
The LVD control register selects four separate threshold values for generating a LVD interrupt to the NVIC or LVD
reset.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15
LVDEN
LVD enable.
0: Disable.
1: Enable.
R/W
1
14
LVDRSTEN
LVD Reset enable.
0: Disable  Flag.
1: Enable  Reset.
R/W
0
13:7
Reserved
R
0
6:2
LVDINTLVL[1:0]
LVD interrupt level.
01: 2.40V.
10: 3.30V.
Other: Reserved.
R/W
10b
4:3
Reserved
R
0
2:0
LVDRSTLVL[2:0]
LVD reset level.
010: 2.40V.
100: 3.30V.
Other: Reserved.
R/W
010b
3.3.7 External RESET Pin Control register (SYS0_EXRSTCTRL)
Address Offset: 0x1C
Bit
Name
Description
Attribute
Reset
31:1
Reserved
R
0
0
RESETDIS
External RESET pin disable bit.
0: Enable external RESET pin. (P3.8 acts as RESET pin)
1: Disable. (P3.8 acts as GPIO pin)
R/W
1
3.3.8 SWD Pin Control register (SYS0_SWDCTRL)
Address Offset: 0x20
Bit
Name
Description
Attribute
Reset
31:1
Reserved
R
0
0
SWDDIS
SWD pin disable bit.
0: Enable SWD pin. (P3.7 acts as SWDIO pin, P3.6 acts as SWCLK pin)
1: Disable. (P3.7 and P3.6 act as GPIO pins)
R/W
0