SONIX SN32F264 - GPIO Port N Bits Clear Operation Register (Gpion_Bclr) (N=0,1,2,3)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 58 Version 1.5
5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3)
Address offset: 0x28
In order for SW to clear GPIO bits without affecting any other pins in a single write operation, the GPIO bit is cleared if
the corresponding bit in this register is set.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
BCLR[15:0]
Bit clear enable. (x = 0 to 15)
0: No effect on Pn.x.
1: Clear Pn.x.
W
0