SONIX SN32F264 - Ct16 Bn Match Control Register (Ct16 Bn_Mctrl) (N=0); Ct16 Bn Match Control Register (Ct16 Bn_Mctrl) (N=1)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 66 Version 1.5
6.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0)
Address Offset: 0x14
Bit
Name
Description
Attribute
Reset
31:3
Reserved
R
0
2
MR0STOP
Stop MR0: TC and PC will stop and CEN bit will be cleared if MR0
matches TC.
0: Disable.
1: Enable.
R/W
0
1
MR0RST
Enable reset TC when MR0 matches TC.
0: Disable.
1: Enable.
R/W
0
0
MR0IE
Enable generating an interrupt based on CM[2:0] when MR0 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
6.7.7 CT16Bn Match Control register (CT16Bn_MCTRL) (n=1)
Address Offset: 0x14
Bit
Name
Description
Attribute
Reset
31:30
Reserved
R
0
29
MR9STOP
Stop MR9: TC and PC will stop and CEN bit will be cleared if MR9
matches TC.
0: Disable.
1: Enable.
R/W
0
28
MR9RST
Enable reset TC when MR9 matches TC.
0: Disable.
1: Enable.
R/W
0
27
MR9IE
Enable generating an interrupt based on CM[2:0] when MR9 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
26
MR8STOP
Stop MR8: TC and PC will stop and CEN bit will be cleared if MR8
matches TC.
0: Disable.
1: Enable.
R/W
0
25
MR8RST
Enable reset TC when MR8 matches TC.
0: Disable.
1: Enable.
R/W
0
24
MR8IE
Enable generating an interrupt based on CM[2:0] when MR8 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
23
MR7STOP
Stop MR7: TC and PC will stop and CEN bit will be cleared if MR7
matches TC.
0: Disable.
1: Enable.
R/W
0
22
MR7RST
Enable reset TC when MR7 matches TC.
0: Disable.
1: Enable.
R/W
0
21
MR7IE
Enable generating an interrupt based on CM[2:0] when MR7 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
20
MR6STOP
Stop MR6: TC and PC will stop and CEN bit will be cleared if MR6
matches TC.
0: Disable.
R/W
0