SONIX SN32F264 - Page 67

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 67 Version 1.5
1: Enable.
19
MR6RST
Enable reset TC when MR6 matches TC.
0: Disable.
1: Enable.
R/W
0
18
MR6IE
Enable generating an interrupt based on CM[2:0] when MR6 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
17
MR5STOP
Stop MR5: TC and PC will stop and CEN bit will be cleared if MR5
matches TC.
0: Disable.
1: Enable.
R/W
0
16
MR5RST
Enable reset TC when MR5 matches TC.
0: Disable.
1: Enable.
R/W
0
15
MR5IE
Enable generating an interrupt based on CM[2:0] when MR5 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
14
MR4STOP
Stop MR4: TC and PC will stop and CEN bit will be cleared if MR4
matches TC.
0: Disable.
1: Enable.
R/W
0
13
MR4RST
Enable reset TC when MR4 matches TC.
0: Disable.
1: Enable.
R/W
0
12
MR4IE
Enable generating an interrupt based on CM[2:0] when MR4 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
11
MR3STOP
Stop MR3: TC and PC will stop and CEN bit will be cleared if MR3
matches TC.
0: Disable.
1: Enable.
R/W
0
10
MR3RST
Enable reset TC when MR3 matches TC.
0: Disable.
1: Enable.
R/W
0
9
MR3IE
Enable generating an interrupt based on CM[2:0] when MR3 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
8
MR2STOP
Stop MR2: TC and PC will stop and CEN bit will be cleared if MR2
matches TC.
0: Disable.
1: Enable.
R/W
0
7
MR2RST
Enable reset TC when MR2 matches TC.
0: Disable.
1: Enable.
R/W
0
6
MR2IE
Enable generating an interrupt based on CM[2:0] when MR2 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
5
MR1STOP
Stop MR1: TC and PC will stop and CEN bit will be cleared if MR1
matches TC.
0: Disable.
1: Enable.
R/W
0
4
MR1RST
Enable reset TC when MR1 matches TC.
0: Disable.
1: Enable.
R/W
0
3
MR1IE
Enable generating an interrupt based on CM[2:0] when MR1 matches the
value in the TC.
0: Disable.
1: Enable.
R/W
0
2
MR0STOP
Stop MR0: TC and PC will stop and CEN bit will be cleared if MR0
matches TC.
0: Disable.
1: Enable.
R/W
0