SONIX SN32F264 - Ct16 B Nregisters; Ct16 Bn Timer Control Register (Ct16 Bn_Tmrctrl) (N=0,1); Ct16 Bn Timer Counter Register (Ct16 Bn_Tc) (N=0,1); Ct16 Bn Prescale Register (Ct16 Bn_Pre) (N=0,1)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 64 Version 1.5
6.7 CT16Bn REGISTERS
Base Address: 0x4000 0000 (CT16B0)
0x4000 2000 (CT16B1)
6.7.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1)
Address Offset: 0x00
 Note: In order to initial TC and PC correctly, SW shall reset TC and PC by setting CRST to 1, and then
enable counter by setting CRST to 1.
Bit
Name
Description
Attribute
Reset
31:2
Reserved
R
0
1
CRST
Counter Reset.
0: Disable counter reset.
1: Timer Counter and the Prescale Counter are synchronously reset on
the next positive edge of PCLK. This is cleared by HW when the counter
reset operation finishes.
R/W
0
0
CEN
Counter Enable
0: Disable Counter.
1: Enable Timer Counter and Prescale Counter for counting.
CEN bit shall be set at last!
* Always Edge-aligned Up-counting mode
R/W
0
6.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1)
Address Offset: 0x04
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal count. Unless it is reset
before reaching its upper limit, the TC will count up to the value 0x0000FFFF and then wrap back to the value
0x00000000. This event does not cause an interrupt, but a Match register can be used to detect an overflow if needed.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
TC[15:0]
Timer Counter.
R/W
0
6.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1)
Address Offset: 0x08
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
PRE[7:0]
Prescale max value.
R/W
0