SONIX SN32F264 - Table of Contents

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.5
Table of Content
AMENDENT HISTORY ................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW ....................................................................................................................... 10
1.1 FEATURES ...................................................................................................................................... 10
1.2 SYSTEM BLOCK DIAGRAM ........................................................................................................ 12
1.3 CLOCK GENERATION BLOCK DIAGRAM ................................................................................ 13
1.4 PIN ASSIGNMENT ......................................................................................................................... 14
1.5 PIN DESCRIPTIONS ....................................................................................................................... 19
1.6 PIN CIRCUIT DIAGRAMS ............................................................................................................. 21
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 22
2.1 MEMORY MAP ............................................................................................................................... 22
2.2 SYSTEM TICK TIMER ................................................................................................................... 23
2.2.1 OPERATION ............................................................................................................................ 23
2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 24
2.2.3 SYSTICK REGISTERS .............................................................................................................. 24
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL) ................................... 24
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD) ........................................... 24
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL) ............................................ 25
2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 25
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 26
2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 26
2.3.2 NVIC REGISTERS .................................................................................................................... 27
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER) ....................................................... 27
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER) ................................................... 27
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 28
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 28
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7) ............................................... 28
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC) .................................................. 29
2.5 CODE OPTION TABLE .................................................................................................................. 30
2.6 CORE REGISTER OVERVIEW ..................................................................................................... 31
3
3
3
SYSTEM CONTROL............................................................................................................................. 32
3.1 RESET .............................................................................................................................................. 32
3.1.1 POWER-ON RESET (POR) ...................................................................................................... 32
3.1.2 WATCHDOG RESET (WDT RESET) ....................................................................................... 33