SONIX SN32F264 - Page 4

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 1.5
3.1.3 BROWN-OUT RESET............................................................................................................... 33
3.1.3.1 BROWN OUT DESCRIPTION ........................................................................................... 33
3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............................................... 34
3.1.3.3 BROWN-OUT RESET IMPROVEMENT .......................................................................... 34
3.1.4 EXTERNAL RESET .................................................................................................................. 35
3.1.4.1 SIMPLY RC RESET CIRCUIT ........................................................................................... 36
3.1.4.2 DIODE & RC RESET CIRCUIT ......................................................................................... 36
3.1.4.3 ZENER DIODE RESET CIRCUIT ...................................................................................... 37
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT ................................................................................... 37
3.1.4.5 EXTERNAL RESET IC ....................................................................................................... 38
3.1.5 SOFTWARE RESET ................................................................................................................. 38
3.2 SYSTEM CLOCK ............................................................................................................................ 39
3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 39
3.2.1.1 Internal High-speed RC Oscillator (IHRC) .......................................................................... 39
3.2.1.2 Internal Low-speed RC Oscillator (ILRC) ........................................................................... 39
3.2.2 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 40
3.2.3 CLOCK-OUT CAPABITITY ..................................................................................................... 40
3.3 SYSTEM CONTROL REGISTERS 0 .............................................................................................. 41
3.3.1 Analog Block Control register (SYS0_ANBCTRL) ................................................................... 41
3.3.2 Clock Source Status register (SYS0_CSST) .............................................................................. 41
3.3.3 System Clock Configuration register (SYS0_CLKCFG) .......................................................... 41
3.3.4 AHB Clock Prescale register (SYS0_AHBCP) ......................................................................... 42
3.3.5 System Reset Status register (SYS0_RSTST) ............................................................................ 42
3.3.6 LVD Control register (SYS0_LVDCTRL) ................................................................................. 43
3.3.7 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 43
3.3.8 SWD Pin Control register (SYS0_SWDCTRL) ......................................................................... 43
3.3.9 Interrupt Vector Table Mapping register (SYS0_IVTM) .......................................................... 44
3.3.10 Noise Detect Control register (SYS0_NDTCTRL).................................................................... 44
3.3.11 Noise Detect Status register (SYS0_NDTSTS) .......................................................................... 44
3.3.12 Anti-EFT Ability Control register (SYS0_ANTIEFT) ............................................................... 44
3.4 SYSTEM CONTROL REGISTERS 1 .............................................................................................. 46
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN) .................................................................... 46
3.4.2 APB Clock Prescale register 1 (SYS1_APBCP1) ..................................................................... 47
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SYSTEM OPERATION MODE ........................................................................................................... 48
4.1 OVERVIEW ..................................................................................................................................... 48
4.2 NORMAL MODE ............................................................................................................................ 48
4.3 LOW-POWER MODES ................................................................................................................... 48
4.3.1 SLEEP MODE .......................................................................................................................... 48