SONIX SN32F264 - APB Clock Prescale Register 1 (SYS1_APBCP1)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 47 Version 1.5
0: Disable
1: Enable
3.4.2 APB Clock Prescale register 1 (SYS1_APBCP1)
Address Offset: 0x08
 Note: Must reset the corresponding peripheral with SYS1_PRST register after changing the prescale
value.
Bit
Name
Description
Attribute
Reset
31
Reserved
CT16B2 clock source prescaler
I2C1 clock source prescaler
R
0
30:28
CLKOUTPRE
[2:0]
Clock-out source prescaler.
000: Clock-out source / 1.
001: Clock-out source / 2.
010: Clock-out source / 4.
011: Clock-out source / 8.
100: Clock-out source / 16.
101: Clock-out source / 32.
110: Clock-out source / 64.
111: Clock-out source / 128.
Other: Reserved
R/W
0
27:23
Reserved
R
0
22:20
WDTPRE[2:0]
WDT clock source prescaler.
000: WDT_PCLK = WDT clock source / 1.
001: WDT_PCLK = WDT clock source / 2.
010: WDT_PCLK = WDT clock source / 4.
011: WDT_PCLK = WDT clock source / 8.
100: WDT_PCLK = WDT clock source / 16.
101: WDT_PCLK = WDT clock source / 32.
Other: Reserved
R/W
0
19:18
Reserved
R
0
17:16
SYSTICKPRE[1:0]
SysTick clock source prescaler
00: SysTick_PCLK = HCLK / 1.
01: SysTick_PCLK = HCLK / 2.
10: SysTick_PCLK = HCLK / 4.
11: SysTick_PCLK = HCLK / 8.
R/W
0
15:0
Reserved
R
0