SONIX SN32F264 - Spi Registers; SPI N Control Register 0 (Spin_Ctrl0) (N=0)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 92 Version 1.5
8.6 SPI REGISTERS
Base Address: 0x4001 C000 (SPI0)
8.6.1 SPI n Control register 0 (SPIn_CTRL0) (n=0)
Address Offset:0x00
 Note:
 1. Must reset SPI FSM with FRESET[1:0] after changing any configuration of SPI when SSPEN = 1.
 2. HW will switch I/O configurations refer to FORMAT bit directly when SSPEN = 1.
Bit
Name
Description
Attribute
Reset
31:19
Reserved
R
0
18
SELDIS
Auto-SEL disable bit. For SPI mode only.
0: Enable Auto-SEL flow control.
1: Disable Auto-SEL flow control.
R/W
1
17:15
RXFIFOTH[2:0]
RX FIFO Threshold level
000: RX FIFO threshold level = 0.
001: RX FIFO threshold level = 1.
…
…
111: RX FIFO threshold level = 7.
R/W
000b
14:12
TXFIFOTH[2:0]
TX FIFO Threshold level
000: TX FIFO threshold level = 0.
001: TX FIFO threshold level = 1.
…
…
111: TX FIFO threshold level = 7.
R/W
000b
11:8
DL[3:0]
Data length = DL[3:0] + 1.
0000~0001: Reversed.
0010: data length = 3.
…
…
1110: data length = 15.
1111: data length = 16.
R/W
1111b
7:6
FRESET[1:0]
SPI FSM and FIFO Reset bit.
00: No effect.
01: Reserved.
10: Reserved.
11: Reset finite state machine and FIFO. (BUF_BUSY = 0, data in shift
BUF is cleared, TX_EMPTY = 1, TX_FULL = 0, RX_EMPTY = 1,
RX_FULL = 0, and data in FIFO is cleared). This bit will be cleared by
HW automatically.
W
0
5
Reserved
R
0
4
FORMAT
Interface format.
0: SPI.
1: Reserved.
R/W
0
3
MS
Master/Slave selection bit.
0: Act as Master.
1: Act as Slave.
R/W
0
2
SDODIS
Slave data output disable bit. (ONLY used in slave mode)
0: Enable slave data output.
1: Disable slave data output. (MISO=0)
R/W
0
1
LOOPBACK
Loop back mode enable.
0: Disable.
1: Data input from data output.
R/W
0
0
SSPEN
SPI enable bit.
0: Disable.
R/W
0