SONIX SN32F264 - Timer Operation; Edge-Aligned Up-Counting Mode

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 61 Version 1.5
6.5 TIMER OPERATION
6.5.1 Edge-aligned Up-counting Mode
The following figure shows a timer configured to reset the count and generate an interrupt on match. The
CT16Bn_PRE register is set to 2, and the CT16Bn_MRx register is set to 6. At the end of the timer cycle where the
match occurs, the timer count is reset. This gives a full length cycle to the match value. The interrupt indicating that a
match occurred is generated in the next clock after the timer reached the match value.
PCLK
CT16Bn_PC
CT16Bn_TC
TC Reset
Interrupt
2
0 1
2
0 1 2
0
4
5
6 0
The following figure shows a timer configured to stop and generate an interrupt on match. The CT16Bn_PRE register is
set to 2, and the CT16Bn_MRx register is set to 6. In the next clock after the timer reaches the match value, the CEN
bit in CT16Bn_TMRCTRL register is cleared, and the interrupt indicating that a match occurred is generated.
PCLK
CT16Bn_PC
CT16Bn_TC
CEN bit
Interrupt
2
0 1
2
0
4
5
6
1
0