SONIX SN32F264 - PWM IO Enable Register (Ct16 Bn_Pwmioenb) (N=1 )

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 79 Version 1.5
10
PWM10EN
PWM10 enable.
0: CT16Bn_PWM10 is controlled by EM10.
1: PWM mode is enabled for CT16Bn_PWM10.
R/W
0
9
PWM9EN
PWM9 enable.
0: CT16Bn_PWM9 is controlled by EM9.
1: PWM mode is enabled for CT16Bn_PWM9.
R/W
0
8
PWM8EN
PWM8 enable.
0: CT16Bn_PWM8 is controlled by EM8.
1: PWM mode is enabled for CT16Bn_PWM8.
R/W
0
7
PWM7EN
PWM7 enable.
0: CT16Bn_PWM7 is controlled by EM7.
1: PWM mode is enabled for CT16Bn_PWM7.
R/W
0
6
PWM6EN
PWM6 enable.
0: CT16Bn_PWM6 is controlled by EM6.
1: PWM mode is enabled for CT16Bn_PWM6.
R/W
0
5
PWM5EN
PWM5 enable.
0: CT16Bn_PWM5 is controlled by EM5.
1: PWM mode is enabled for CT16Bn_PWM5.
R/W
0
4
PWM4EN
PWM4 enable.
0: CT16Bn_PWM4 is controlled by EM4.
1: PWM mode is enabled for CT16Bn_PWM4.
R/W
0
3
PWM3EN
PWM3 enable.
0: CT16Bn_PWM3 is controlled by EM3.
1: PWM mode is enabled for CT16Bn_PWM3.
R/W
0
2
PWM2EN
PWM2 enable.
0: CT16Bn_PWM2 is controlled by EM2.
1: PWM mode is enabled for CT16Bn_PWM2.
R/W
0
1
PWM1EN
PWM1 enable.
0: CT16Bn_PWM1 is controlled by EM1.
1: PWM mode is enabled for CT16Bn_PWM1.
R/W
0
0
PWM0EN
PWM0 enable.
0: CT16Bn_PWM0 is controlled by EM0.
1: PWM mode is enabled for CT16Bn_PWM0.
R/W
0
6.7.20 PWM IO Enable register (CT16Bn_PWMIOENB) (n=1 )
Address Offset: 0xA0
The PWM Control register is used to configure the match outputs as PWM outputs. Each match output can be
independently set to perform either as PWM output or as match output whose function is controlled by CT16Bn_EM
register.
For each timer, a maximum of 4 single edge controlled PWM outputs can be selected on the CT16Bn_PWMCTRL[3:0]
outputs. One additional match register determines the PWM cycle length. When a match occurs in any of the other
match registers, the PWM output is set to HIGH. The timer is reset by the match register that is configured to set the
PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured as PWM outputs are
cleared.
Bit
Name
Description
Attribute
Reset
31:23
Reserved
R
0
22
PWM22IOEN
CT16Bn_PWM22/GPIO selection bit.
0: CT16Bn_PWM22 pin act as GPIO.
1: CT16Bn_PWM22 pin act as match output, and output signal depends
on PWM22EN bit.
R/W
0
21
PWM21IOEN
CT16Bn_PWM21/GPIO selection bit.
0: CT16Bn_PWM21 pin act as GPIO.
1: CT16Bn_PWM21 pin act as match output, and output signal depends
on PWM21EN bit.
R/W
0
20
Reserved
R
0
19
PWM19IOEN
CT16Bn_PWM19/GPIO selection bit.
0: CT16Bn_PWM19 pin act as GPIO.
1: CT16Bn_PWM19 pin act as match output, and output signal depends
on PWM19EN bit.
R/W
0