SONIX SN32F264 - Spi; Overview; Features; Pin Description

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 88 Version 1.5
8
8
8
SPI
8.1 OVERVIEW
The SPI controller can interact with multiple masters and slaves on the bus. Only a single master and a single slave
can communicate on the bus during a given data transfer. Data transfers are in principle full duplex, with frames of 4 to
16 bits of data flowing from the master to the slave and from the slave to the master. In practice it is often the case that
only one of these data flows carries meaningful data.
8.2 FEATURES
 Compatible with Motorola SPI bus.
 Synchronous Serial Communication.
 Supports master or slave operation.
 8-frame FIFO for both transmitter and receiver.
 4-bit to 16-bit frame.
 Maximum SPI speed of 24 Mbps (master) or 6 Mbps. (slave)
 Data transfer format is from MSB or LSB controlled by register.
 The start phase of data sampling location selection is 1
st
-phase or 2
nd
-phase controlled register.
8.3 PIN DESCRIPTION
Pin Name
Type
Description
GPIO Configuration
SCKn
O
SPI Serial clock (Master)
I
SPI Serial clock (Slave)
Depends on GPIOn_CFG
SELn
O
SPI Slave Select/SSI Frame Sync (Master)
I
SPI Slave Select (Slave)
Depends on GPIOn_CFG
MISOn
I
Master In Slave Out (Master)
Depends on GPIOn_CFG
O
Master In Slave Out (Slave)
MOSIn
O
Master Out Slave In (Master)
I
Master Out Slave In (Slave)
Depends on GPIOn_CFG