SONIX SN32F264 - I2 C N TX Data Register (I2 Cn_Txdata) (N=0); I2 C N RX Data Register (I2 Cn_Rxdata) (N=0); I2 C N Slave Address 0 Register (I2 Cn_Slvaddr0) (N=0); I2 C N Slave Address 1~3 Register (I2 Cn_Slvaddr1~3) (N=0)

SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 102 Version 1.5
SLAVE modea STOP condition was received.
2
NACK_STAT
NACK done status.
0 : Not received a NACK.
1 : Received a NACK.
R
0
1
ACK_STAT
ACK done status.
0 : Not received an ACK.
1 : Received an ACK.
R
0
0
RX_DN
RX done status.
0: No RX with ACK/NACK transfer.
1: 8-bit RX with ACK/NACK transfer is done.
R
0
9.7.3 I2C n TX Data register (I2Cn_TXDATA) (n=0)
Address Offset: 0x08
This register contains the data to be transmitted.
In Master TX mode, CPU writes this register will trigger a TX function. In Slave TX mode, CPU has to write this register
before next TX procedure.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
DATA[7:0]
Data to be transmitted.
R/W
0x00
9.7.4 I2C n RX Data register (I2Cn_RXDATA) (n=0)
Address Offset: 0x0C
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7:0
DATA[7:0]
Contains the data received. Read this register when RX_DN = 1.
R
0x00
9.7.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0)
Address Offset: 0x10
Only used in slave mode. In master mode, this register has no effect.
If this register contains 0x00, the I2C will not acknowledge any address on the bus. Register ADR0 to ADR3 will be
cleared to this disabled state on reset.
Bit
Name
Description
Attribute
Reset
31:10
ADD_MODE
Slave address mode.
0 : 7-bit address mode.
1: 10-bit address mode.
RW
0
30
GCEN
General call address enable bit..
0: Disable.
1: Enable general call address. (0x0)
RW
0
29:10
Reserved
R
0
9:0
ADDR[9:0]
The I2C slave address.
ADD[9:0] is valid when ADD_MODE = 1.
ADD[7:1] is valid when ADD_MODE = 0.
R/W
0
9.7.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0)
Address Offset: 0x14, 0x18, 0x1C