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SONIX SN32F264 - GPIO Port N Interrupt Enable Register (Gpion_Ie) (N=0,1,2,3); GPIO Port N Raw Interrupt Status Register (Gpion_Ris) (N=0,1,2,3); GPIO Port N Interrupt Clear Register (Gpion_Ic) (N=0,1,2,3); GPIO Port N Bits Set Operation Register (Gpion_Bset) (N=0,1,2,3)

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SN32F260 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 57 Version 1.5
1: Depending on setting in register GPIOn_IS, Falling edges or LOW level
on Pn.x trigger an interrupt.
5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3)
Address offset: 0x18
Bits set to HIGH in the GPIOn_IE register allow the corresponding pins to trigger their individual interrupts. Clearing a
bit disables interrupt triggering on that pin.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IE[15:0]
Selects interrupt on pin x to be enabled. (x = 0 to 15)
0: Disable Interrupt on Pn.x.
1: Enable Interrupt on Pn.x.
R/W
0
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3)
Address offset: 0x1C
This register indicates the status for GPIO control raw interrupts. A GPIO interrupt is sent to the interrupt controller if
the corresponding bit in GPIOn_IE register is set.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IF[15:0]
GPIO raw interrupt flag. (x = 0 to 15)
0: No interrupt on Pn.x.
1: Interrupt requirements met on Pn.x.
R
0
5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3)
Address offset: 0x20
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
IC[15:0]
Selects interrupt flag on pin x to be cleared. (x = 0 to 15)
0: No effect.
1: Clear interrupt flag on Pn.x.
W
0
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3)
Address offset: 0x24
In order for SW to set GPIO bits without affecting any other pins in a single write operation, the GPIO bit is set if the
corresponding bit in the GPIOn_BSET register is set.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15:0
BSET[15:0]
Bit Set enable. (x = 0 to 15)
0: No effect on Pn.x.
1: Set Pn.x to “1”.
W
0

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