Sun Microsystems SPARC classic - Page 45

Chapter 3 Power-On Self-Test (POST) 3-7
FPU SP Inexact CEXC Test
FPU SP Trap Priority > Test
FPU SP Trap Priority < Test
FPU DP Invalid CEXC Test
FPU DP Overflow CEXC Test
FPU DP Divide-by-0 CEXC Test
FPU DP Inexact CEXC Test
FPU DP Trap Priority > Test
FPU DP Trap Priority < Test
PROC0 Interrupt Regs Tests
Soft Interrupts OFF Test
Soft Interrupts ON Test
PROC0 User Timer Test
PROC0 Counter/Timer Test
DMA2 E_CSR Register Test
LANCE Address Port Tests
LANCE Data Port Tests
DMA2 D_CSR Register Test
DMA2 D_ADDR Register Test
DMA2 D_BCNT Register Test
DMA2 D_NADDR Register Test
ESP Registers Tests
DMA2 P_CSR Register Test
DMA2 P_ADDR Register Test
DMA2 P_BCNT Register Test
PPORT Registers Tests
NVRAM Access Test
TOD Registers Test
TABLE 3-2 Listing of POST Tests (Continued)