Theory of Operation
3-2 SPG600 & SPG300 Sync Pulse Generators Service Manual
Analog Genlock
The analog genlock consists of the following blocks:
Genlock Controller. This block controls the A/D converter, memory, and sync
separator to obtain correct digital data.
A/D Converter. The A/D converter digitizes the analog input signal to 10-bits digital
data for genlock operation. This data is read by the CPU and used to control the
master oscillator frequency.
Sync Separator. The sync separator separates the sync signal such as H sync or V
sync from the input signal.
Amp & Restorer. This block consists of amplifiers to adjust the amplitude of the
signal from the REF input and restorer to recover the DC component of the signal.
Analog Generator (A10
Main Board Only)
The analog generator consists of the following blocks:
Sync Memory. The sync memory is a part of the FPGA and keeps the data of the
sync pulses.
Line Memory. The line memory is a part of the FPGA and contains the active part
of the line data of the test signal. It can store up to four line data.
Frame Memory. The frame memory contains a series of pointers that control the
order of the video lines stored in the Line Memory, which are used to produce
digital signals.
Overlay Memory. The overlay memory generates timings to multiplex the line
memory data and the overlay data used for an ID text and logo overlay.
Delay Counter. The delay counter in the FPGA sets the timing of each channel. The
optional fine timing feature is achieved by digital filter technique.
Signal Generator. This block builds complete test signal sequence with sync and
line data according to the frame memory.
D/A Converter and Amplifier. This block consists of a D/A converter, an amplifier,
and a filter. It converts the digital data from the Signal Generator to an analog
signal and reconstructs the signal for output.
SDI Generator
The SDI generator consists of the following blocks:
Sync Memory. The sync memory is a part of the FPGA and stores the EAV and
SAV data.
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