SPG600 & SPG300 Sync Pulse Generators Service Manual 3-1
Theory of Operation
This section describes the basic operation of the major circuit blocks or modules in
the sync pulse generator. The Diagram section, beginning on page 9-1, includes
block diagrams and interconnect diagrams.
A10 Main Board (SPG600) and A50 Main Board (SPG300)
The A10/A50 Main board consists of the following blocks:
Master Clock Oscillator
This block generates a master clock signal. It is generated from the 13.5 MHz
OCXO with high accuracy. The frequency is controlled by a 16-bit D/A converter.
Audio Clock
This block generates a 12.7 MHz clock for AES/EBU audio. The clock is phase
locked to 13.5 MHz master oscillator.
Video Clock
This block generates a 27 MHz clock for video signals. The clock is phase locked
to the 13.5 MHz master clock.
Frame Reset
This block generates a 15/1.001 Hz frame reset signal for the NTSC standard and
a 6.25 Hz frame reset signal for the PAL standard.
D/A Converter
The 16-bit D/A converter controls the master clock oscillator frequency.
CPU
The CPU manages all functions in the sync pulse generator.
Flash Memory and SDRAM
This block consists of an 8 MB flash memory and a 16 MB SDRAM. The flash
memory holds the data for system boot (1 MB) and the program code (7 MB).
Parallel to Serial Converter
This block converts the CPU parallel bus to the original serial bus.
GPI Interface
This block controls the general purpose interface. The interface is used to recall a
preset and output an alarm signal.
Network Interface
This block controls the Ethernet interface for Web and SNMP application. The
sync pulse generator has a 100 BASE-T connector on the rear panel.
DC/DC Converter
This block converts the +5 V power, supplied by the Power Supply Module, to
-5 V, 3.3 V, 8 V, and 12 V.
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