Xilinx Virtex-5 RocketIO GTP User Manual

20 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 1: Introduction to the RocketIO GTP Transceiver
R
GTP transceivers are placed as dual transceiver GTP_DUAL tiles in Virtex-5 LXT and SXT
Platform devices. This configuration allows two transceivers to share a single PLL with the
TX and RX functions of both, reducing size and power consumption.
Figure 1-1 shows GTP_DUAL placement in an example Virtex-5 device (XCV5LX110T).
Additional information on the functional blocks in Figure 1-1 is available in the following
locations:
• Chapter 8, “Cyclic Redundancy Check (CRC),” provides more details on the CRC
blocks in Figure 1-1.
• The Virtex-5 Configuration Guide provides more on the Config and Clock, CMT, and
I/O blocks.
• The Virtex-5 Ethernet MAC User Guide provides detailed information on the Ethernet
MAC.
• The Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs provides
detailed information on PCI Express compliance.
10GFC 3.1875 Gb/s
SDI
HD-SDI
DVB-ASI
143/176/270/360 Mb/s
1.485/1.4835 Gb/s
270 Mb/s
10G Base-CX4 802.3ak/D4.0 3.125 Gb/s
Gigabit Ethernet (1000BASE-CX
802.3z/D5.0)
1.25 Gb/s
SATA Gen 1/II (Rev 1.0a)
SATA Gen. 2 (Rev 1.0a)
1.5 Gb/s
3.0 Gb/s
• Rate negotiation for Gen 2 (entire link operates at
Gen 1/Gen 2 speeds)
• LOS
• OOB Beacon
SAS Rev 5 1.5/3.0 Gb/s
Serial RapidIO 1.25/2.5/3.125 Gb/s
CPRI (Ver 2.0) 614.4/1228.8/2457.6 Mb/s
Infiniband (Volume 2 Release 1.1) 2.5 Gb/s
SFI-5 2.488 – 3.125 Gb/s • Synchronous clocking (bypass FIFOs)
OBSAI RP3 (Spec Issue 1.0)
(1)
768/1536/3072 Mb/s
Aurora 100 Mb/s – 3.2 Gb/s
Table 1-1: List of Standards Supported by the GTP_DUAL Tile (Continued)
Protocols Supported
Protocol Data Rates
Supported
Miscellaneous Features

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English